FIG. 3 is a block diagram illustrating an exemplary internal configuration of a conventional semiconductor apparatus.
A semiconductor apparatus 100 shown in FIG. 3 functions as an ID tag and includes a semiconductor chip 101 which functions as an RFID chip. The semiconductor apparatus 100 operates on electricity supplied by electromagnetic waves received by an antenna 102. The electromagnetic waves received by the antenna 102 are rectified by a rectifying circuit (not shown) in analog circuitry 111. An internal voltage generating circuit 121, which functions as a voltage regulator, generates different constant voltages, an internal voltage VCC and an internal voltage VDD, from a voltage obtained by rectification. The internal voltage VCC provides electricity for the analog circuitry 111; and the internal voltage VDD provides electricity for memory circuitry 113, digital circuitry 112 for controlling the operation of the memory circuitry 113, and I/O cells 114 through 117.
The semiconductor chip 101 includes pads Pvcc and Pvdd used for checking the internal voltages VCC and VDD generated in the semiconductor chip 101 from the outside. The internal voltage VCC is applied to the pad Pvcc, and the internal voltage VDD is applied to the pad Pvdd.
FIG. 4 is a block diagram illustrating another exemplary internal configuration of the semiconductor apparatus 100. The internal configuration shown in FIG. 4 differs from that shown in FIG. 3 in that a selection circuit 125 is added. Both the internal voltages VCC and VDD are input into the selection circuit 125. The selection circuit 125 outputs either the internal voltage VCC or VDD to a pad Pv according to a control signal Sc input via a pad Psc from the outside.
Patent document 1 discloses a core LSI created with a core CPU and prepared cell libraries according to a gate array or standard cell approach. Patent document 2 discloses a semiconductor integrated circuit apparatus the configuration of which makes it possible to accurately and easily test its internal voltages without increasing its consumption current and the number of pads.
[Patent document 1] Japanese Patent Application Publication No. 61-207030
[Patent document 2] Japanese Patent Application Publication No. 11-66890
However, in a conventional apparatus such as the semiconductor apparatus 100, each pad may have a size of, for example, 100 μm square where the semiconductor chip 101 has a size of 2 mm square. Since pads occupy much space on the semiconductor chip 101, it is necessary to reduce the number of pads to reduce the size of the semiconductor chip 101 and thereby reduce the production costs.